A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology

Abstract

This brief presents a 100-Gb/s eight-level pulse amplitude modulation (PAM-8) transmitter (TX) for next-generation wireline communication systems. The high-swing hybrid driver combines the cascode current-mode logic (CML) and tailless CML techniques for higher bandwidth, output resistance, and wide feed-forward equalizer (FFE) tap control range. The transmitter employs a reconfigurable 3-tap FFE for adaptive channel equalization. The design achieves a 100-Gb/s data rate with worst-case eye-opening values of 52 mV with FFE and 1.5-V peak-to-peak differential (Vppd) output swing without FFE. The transmitter test chip is fabricated in a 40-nm CMOS technology and the measured energy efficiency is 4.42 pJ/bit.