Engineering Negative Capacitance in Hf0.5Zr0.5O2 for Low-Power and Reliable Charge Trap Flash Memory

Abstract

Charge trap flash (CTF) memory has emerged as a key solution for high-density nonvolatile memory. However, the high operating voltage of CTF memory leads to critical reliability issues, such as cell-to-cell interference and dielectric breakdown, limiting further pitch size scaling in 3D architectures. Here, we report a negative capacitance charge trap flash (NC-CTF) memory that exhibits remarkable operation efficiency by using the NC-induced capacitance boosting effect of Hf0.5Zr0.5O2 (HZO) layer. To strengthen the NC effect and enable low-voltage program/erase (PGM/ERS) operations, we engineered the HZO layer by incorporating a dielectric interlayer (IL). The IL modulates the domain configuration within HZO, thereby enhancing the depolarization energy and stabilizing the NC state. Furthermore, adopting AlN as the IL material and employing a superlattice-based deposition process for HZO promoted the formation of oxygen vacancies and a spatial confinement effect, which collectively reduced the energy barrier for orthorhombic phase formation and enhanced ferroelectricity even at a halved thickness enabled by IL insertion. By embedding the engineered NC layer into the blocking oxide (BO), the NC-CTF achieves low voltage PGM/ERS operation while simultaneously addressing reliability concerns. These synergistic improvements pave the way for practical implementation of NC-CTF as a promising candidate for high-density, next-generation nonvolatile memory.