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Physics-Based α-IGZO TFTs Compact Modeling and Neural Network Application with 2T0C DRAM Cell
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Hyoungsoo | - |
| dc.contributor.author | Park, Eunchan | - |
| dc.contributor.author | Kwak, Been | - |
| dc.contributor.author | Kwon, Daewoong | - |
| dc.contributor.author | Kim, Hyunwoo | - |
| dc.date.accessioned | 2026-01-23T02:30:17Z | - |
| dc.date.available | 2026-01-23T02:30:17Z | - |
| dc.date.issued | 2025-09 | - |
| dc.identifier.issn | 2169-3536 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/210447 | - |
| dc.description.abstract | Advanced amorphous oxide devices such as amorphous InGaZnO (α-IGZO) operate based on mechanisms that differ significantly from those of conventional Si-based devices, primarily due to structural differences. While both types of devices utilize field-effect mobility as the primary mode of charge transport, there is no consensus on the additional complexities involved in charge movement within α-IGZO devices, which arise from their unique material properties. The BSIM series model commonly used for silicon devices cannot fully explain the charge transport mechanism of α-IGZO devices. Unfortunately, physics-based compact models for α-IGZO, which reflect the intrinsic nature of charge transport involved in electrical conduction have not been completely proposed with a standard formula. This paper presents a compact model for α-IGZO TFTs that incorporates charge transport mechanisms such as percolation, Variable-Range Hopping (VRH), and Trap-Limited Conduction (TLC), along with a methodology for calculating surface potential using the Lambert W function. The model is implemented in Verilog-A for circuit-level simulation and provides high accuracy with fabricated devices measurement. The model’s performance is further evaluated using the MNIST dataset by comparing the classification accuracy across various shallow-layer neural network architectures, demonstrating the model’s potential in neuromorphic system applications. | - |
| dc.format.extent | 12 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
| dc.title | Physics-Based α-IGZO TFTs Compact Modeling and Neural Network Application with 2T0C DRAM Cell | - |
| dc.type | Article | - |
| dc.publisher.location | 미국 | - |
| dc.identifier.doi | 10.1109/ACCESS.2025.3605345 | - |
| dc.identifier.scopusid | 2-s2.0-105015154581 | - |
| dc.identifier.wosid | 001574223700033 | - |
| dc.identifier.bibliographicCitation | IEEE ACCESS, v.13, pp 158751 - 158762 | - |
| dc.citation.title | IEEE ACCESS | - |
| dc.citation.volume | 13 | - |
| dc.citation.startPage | 158751 | - |
| dc.citation.endPage | 158762 | - |
| dc.type.docType | Article in press | - |
| dc.description.isOpenAccess | Y | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalResearchArea | Telecommunications | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalWebOfScienceCategory | Telecommunications | - |
| dc.subject.keywordPlus | THIN-FILM TRANSISTORS | - |
| dc.subject.keywordPlus | GATE | - |
| dc.subject.keywordAuthor | Electron traps | - |
| dc.subject.keywordAuthor | Integrated circuit modeling | - |
| dc.subject.keywordAuthor | Electrons | - |
| dc.subject.keywordAuthor | Semiconductor device modeling | - |
| dc.subject.keywordAuthor | Mathematical models | - |
| dc.subject.keywordAuthor | Accuracy | - |
| dc.subject.keywordAuthor | Logic gates | - |
| dc.subject.keywordAuthor | Electric potential | - |
| dc.subject.keywordAuthor | Fermi level | - |
| dc.subject.keywordAuthor | Tunneling | - |
| dc.subject.keywordAuthor | InGaZnOx (IGZO) | - |
| dc.subject.keywordAuthor | compact model | - |
| dc.subject.keywordAuthor | neural network | - |
| dc.subject.keywordAuthor | oxide TFT | - |
| dc.subject.keywordAuthor | verilog | - |
| dc.subject.keywordAuthor | spice and simulation | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/11151167 | - |
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