A 6-GS/s 8-bit Time-Domain ADC With Selection-First Pipelined Successive Approximation Register TDC in 28-nm CMOS Technology

Abstract

This brief presents a single-channel 8-bit time-domain analog-to-digital converter (TD-ADC) that employs a selection-first successive approximation register (SAR) time-to-digital converter (TDC) to address key limitations of prior TDC designs used in TD-ADCs. By adopting the selection-first approach, each bit decision requires only one reference delay path per bit, improving metastability tolerance compared to conventional computation-first designs. Moreover, the proposed TDC eliminates input-dependent errors and reduces the vulnerability to time-comparator mismatches observed in gate-based TDCs. Fabricated in 28-nm CMOS technology, the prototype TD-ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 36.4 dB for a Nyquist-rate input at 6 GS/s while consuming 51 mW.