2C-Ternary Content Addressable Memory in Memcapacitor Crossbar Array with NAND Flash Structure
- Authors
- Hwang, Hwiho; Yu, Junsu; Youn, Sangwook; Choi, Woo Young; Kim, Hyungjin
- Issue Date
- Mar-2025
- Publisher
- WILEY-V C H VERLAG GMBH
- Keywords
- crossbar array; in-memory computing; memcapacitor; NAND flash; ternary content addressable memory (TCAM)
- Citation
- SMALL, v.21, no.9, pp 1 - 11
- Pages
- 11
- Indexed
- SCIE
SCOPUS
- Journal Title
- SMALL
- Volume
- 21
- Number
- 9
- Start Page
- 1
- End Page
- 11
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/211065
- DOI
- 10.1002/smll.202408618
- ISSN
- 1613-6810
1613-6829
- Abstract
- As one of the data-intensive in-memory computing hardware, ternary content addressable memory (TCAM) stands out for its efficient in-memory-searching capability, enabling high-throughput and low-latency computing. However, TCAMs, especially those based on resistive non-volatile memories, face challenges in limited resistance ratio (Rhigh/Rlow) that deteriorate sensing margin and energy efficiency. Addressing these issues, a TCAM cell composed of two memcapacitors (2C-TCAM) based on NAND flash array structure is proposed. The 2C-TCAM utilizes the memcapacitors coupled with the mature technology of flash cells for reliable operation and high-density (8F2) array configuration. Thanks to the capacitive readout of memcapacitors, the 2C-TCAM achieves near-zero static power consumption and minimizes IR drop effect. Consequently, highly parallel and reliable search functionality can be obtained even in large arrays while preserving the sensing margin. Electrical characteristics and operation schemes of the proposed 2C-TCAM cell are validated through fabrication and measurements, and array operations are experimentally demonstrated using a 24 x 48 memcapacitor crossbar array with sensing circuits. Additionally, the system-level performance of the 2C-TCAM array is analyzed, considering the device programming accuracy. Search times of 47 ps and energy consumption of 11.7 fJ per bit are achieved by scaling down the device cell area to 1 mu m2.
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