Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Roh, Si-Dong | - |
dc.contributor.author | Cho, Keol | - |
dc.contributor.author | Chung, Ki-Seok | - |
dc.date.accessioned | 2021-08-02T15:51:26Z | - |
dc.date.available | 2021-08-02T15:51:26Z | - |
dc.date.created | 2021-05-11 | - |
dc.date.issued | 2017-02 | - |
dc.identifier.issn | 2159-3442 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/21206 | - |
dc.description.abstract | As modern hardware architectures are complicated, designing hardware systems is challenging. High level synthesis (HLS) has emerged as an effective hardware synthesis method that saves the engineering cost and the design time. Meanwhile, field programmable gate array (FPGA) devices have been improved significantly in terms of both performance and power efficiency, and therefore, they are often considered as an alternative hardware implementation to application specific integrated circuits (ASICs). SDSoC is a C/C++ development environment which enables developers to leverage both configurable hardware and software implementations. This paper introduces a hardware-software co-design of low density parity check (LDPC) decoding synthesized by SDSoC for a heterogeneous FPGA and central processing unit (CPU) platform. The LDPC code is one of the strongest error correcting codes. In order to optimize performance, the LDPC decoding process is divided into several stages. Then, either software or FPGA implementation is selected based on algorithmic characteristics and data dependencies of each stage. For stages which are implemented on the FPGA device, loop unrolling and loop pipelining techniques are applied. Compared to a pure software decoder, the proposed LDPC decoder achieved a speed-up of 4.41 while maintaining the software decoder's BER performance and flexibility for various standards | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | Implementation of an LDPC decoder on a heterogeneous FPGA-CPU platform using SDSoC | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Chung, Ki-Seok | - |
dc.identifier.doi | 10.1109/TENCON.2016.7848497 | - |
dc.identifier.scopusid | 2-s2.0-85015362856 | - |
dc.identifier.bibliographicCitation | IEEE Region 10 Annual International Conference, Proceedings/TENCON, pp.2555 - 2558 | - |
dc.relation.isPartOf | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.title | IEEE Region 10 Annual International Conference, Proceedings/TENCON | - |
dc.citation.startPage | 2555 | - |
dc.citation.endPage | 2558 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Codes (symbols) | - |
dc.subject.keywordPlus | Cost engineering | - |
dc.subject.keywordPlus | Decoding | - |
dc.subject.keywordPlus | Error correction | - |
dc.subject.keywordPlus | Field programmable gate arrays (FPGA) | - |
dc.subject.keywordPlus | Forward error correction | - |
dc.subject.keywordPlus | Hardware | - |
dc.subject.keywordPlus | Hardware-software codesign | - |
dc.subject.keywordPlus | High level synthesis | - |
dc.subject.keywordPlus | Information theory | - |
dc.subject.keywordPlus | Integrated circuit design | - |
dc.subject.keywordPlus | Logic Synthesis | - |
dc.subject.keywordPlus | Program processors | - |
dc.subject.keywordPlus | Satellite communication systems | - |
dc.subject.keywordPlus | Configurable hardware | - |
dc.subject.keywordPlus | Development environment | - |
dc.subject.keywordPlus | Error correcting code | - |
dc.subject.keywordPlus | Hardware architecture | - |
dc.subject.keywordPlus | Hardware implementations | - |
dc.subject.keywordPlus | LDPC | - |
dc.subject.keywordPlus | Low density parity check decoding | - |
dc.subject.keywordPlus | SDSoC | - |
dc.subject.keywordPlus | C (programming language) | - |
dc.subject.keywordAuthor | Error correcting code | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | High-level synthesis | - |
dc.subject.keywordAuthor | LDPC | - |
dc.subject.keywordAuthor | SDSoC | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/7848497 | - |
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