Impact of hydrogen-controlled thermal ALD SiO2 insulators on IGZO channel FETs to optimize the electrical performance

Abstract

Oxide semiconductors (OS) are attractive materials for 3D device applications such as monolithic stacked, channel-all-around, and gate-all-around structures, owing to their low off-current, high field-effect mobility, 3D processability, and superior large-area uniformity. However, the electrical and reliability properties of OS channel field effect transistors (FETs) are sensitively affected by gate insulator (GI) conditions, such as hydrogen content. For this reason, a silicon dioxide (SiO2) GI was generally fabricated under sufficient atomic layer deposition (ALD) reaction conditions, such as high deposition temperature, ozone reactant density, or oxygen plasma, to reduce the hydrogen content. However, higher oxidation conditions of ALD reactants lower the conductivity of the IGZO channel at a top-gate FET. Herein, we propose optimizing the properties of FETs by lowering the hydrogen content of a low-temperature deposited thermal ALD SiO2 GI using a post-annealing process. Furthermore, the effects of hydrogen as a mobile ionic charge are presented. The 250 °C deposited SiO2 gate insulator FET exhibits a high field-effect mobility of 21.1 cm2 V−1 s−1, threshold voltage of 0.4 V, and subthreshold swing of 100 mV dec−1 with superior stabilities of −0.19 and +0.25 V shift during positive and negative-bias stress, respectively, by lowering the hydrogen content.