A 108Gb/s PAM-8 CTLE+FFE Receiver Frontend with 1.4Vppd Input Range in 28nm

Abstract

Data-intensive applications have driven the I/O transceiver data rates beyond 100 ~Gb / s per lane, prompting the adoption of higherorder modulation schemes such as PAM-8 for improved bandwidth efficiency [1-8]. However, the multi-level signaling requires high signal power to secure SNR, thereby imposing stringent linearity requirements on the receiver [1]. As channel loss increases, the receivers must use equalization methods beyond the continuous time linear equalizer (CTLE), such as feed-forward equalizers (FFEs) [2-6]. This paper therefore introduces a highly linear receiver frontend system with a 2 -tap FFE capability in 28 nm CMOS, which effectively compensates distortions from > 10 ~dB channel loss at the Nyquist frequency, supporting a data-rate of 108 ~Gb / s with PAM-8 modulationin 28 nm.