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Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kim, Mun-Ju | - |
| dc.contributor.author | Min, Byung-Cheol | - |
| dc.contributor.author | Go, Dong-Jae | - |
| dc.contributor.author | Yun, Seokmin | - |
| dc.contributor.author | Jang, Yooseong | - |
| dc.contributor.author | Han, Jaeduk | - |
| dc.contributor.author | Kim, Kang-Wook | - |
| dc.date.accessioned | 2026-06-10T02:00:11Z | - |
| dc.date.available | 2026-06-10T02:00:11Z | - |
| dc.date.issued | 2026-01 | - |
| dc.identifier.issn | 2165-4107 | - |
| dc.identifier.issn | 2165-4115 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/213203 | - |
| dc.description.abstract | A compact signal integrity recovery module with a CPS-based signal balancing structure is proposed. The proposed module demonstrates rejection of common-mode noise and restoration of signal imbalance from 11.4 GHz to over 20 GHz. | - |
| dc.format.extent | 3 | - |
| dc.language | 영어 | - |
| dc.language.iso | ENG | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | Compact Signal Integrity Recovery Module in Coplanar Stripline with Signal Balancing | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1109/EPEPS63858.2025.11346787 | - |
| dc.identifier.scopusid | 2-s2.0-105033363948 | - |
| dc.identifier.bibliographicCitation | 2025 IEEE 34th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2025, pp 1 - 3 | - |
| dc.citation.title | 2025 IEEE 34th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2025 | - |
| dc.citation.startPage | 1 | - |
| dc.citation.endPage | 3 | - |
| dc.type.docType | Conference paper | - |
| dc.description.isOpenAccess | N | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.subject.keywordPlus | Balancing | - |
| dc.subject.keywordPlus | Electromagnetic compatibility | - |
| dc.subject.keywordAuthor | balanced line | - |
| dc.subject.keywordAuthor | common-mode rejection | - |
| dc.subject.keywordAuthor | signal integrity | - |
| dc.subject.keywordAuthor | ultra-high-speed digital signal | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/11346787/ | - |
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)