Electron-kinetic reactor engineering for damage-free, high-selectivity plasma etching
- Authors
- Kim, Min-Seok; Yeo, Yujin; Nahm, Hyeon Ho; Chung, Chin-Wook
- Issue Date
- Apr-2026
- Publisher
- ELSEVIER SCIENCE SA
- Keywords
- High selectivity; Damage-free etching; Selective dissociation; Radical control; Ultralow electron temperature plasma
- Citation
- CHEMICAL ENGINEERING JOURNAL, v.533, pp 1 - 8
- Pages
- 8
- Indexed
- SCIE
SCOPUS
- Journal Title
- CHEMICAL ENGINEERING JOURNAL
- Volume
- 533
- Start Page
- 1
- End Page
- 8
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/213965
- DOI
- 10.1016/j.cej.2026.173989
- ISSN
- 1385-8947
1873-3212
- Abstract
- Achieving atomic-scale precision in three-dimensional device architectures, such as Gate-All-Around Field-Effect Transistors (GAAFETs), is currently bottlenecked by the inherent trade-off between etch selectivity and plasma-induced damage. Here, we present a scalable and reactor-compatible strategy that kinetically engineers the electron energy distribution to independently tailor radical stoichiometry and ion energy. By integrating a DC-biased grid into a standard inductively coupled plasma (ICP) system, we selectively accelerated electrons to the precise dissociation threshold (∼15 eV) of the precursor gas. This kinetic control enabled the preferential generation of polymerizing CF2 radicals over etchant F atoms, increasing the CF2/F ratio by ∼30%, while simultaneously forming an ultra-low electron temperature (ULET, Te < 1 eV) plasma that suppresses ion-induced damage. Consequently, this dual mechanism facilitated the formation of a robust fluorocarbon passivation layer on SiN, achieving a six-fold improvement in SiO2/SiN selectivity compared to conventional methods. The universality of this approach was further validated by reversing the selectivity in NF3/O2 plasmas through the enhanced production of NO radicals. Validated on nanoscale patterned wafers, this electron-kinetic engineered plasma establishes a practical pathway to overcome the patterning limitations in next-generation semiconductor manufacturing.
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