Front-Side NMOS Connection as the Preferred Scheme: Quantifying the ~10× Resistance Limit of NMOS-Backside in DBC 3DSFET SRAM

Abstract

In 3-Dimensional Stacked FET (3DSFET) technology beyond the 1 nm node, direct backside contact (DBC) has emerged as an effective approach to continue scaling of both logic and SRAM bit cells. Two NMOS connection strategies under DBC integration - backside routing and front-side routing - are analyzed. The hybrid configuration, with PMOS using DBC and NMOS using front-side contact, achieves ~30% SRAM bit cell area reduction and performance gains of 7.2% in PD/PG on-current, 4.7% in IREAD, and 7.2% in Gamma. In contrast, backside NMOS routing increases area and resistance, but reliable operation is preserved as long as resistance growth is limited to ~10×, establishing a practical margin for DBC adoption in future high-density SRAM.