A 12-to-20Gb/s, 2.93-pJ/Bit Jitter-Filtering Retimer with High Input Jitter Tolerance in 28nm CMOS

Abstract

A jitter-filtering retimer is presented with a wide-bandwidth injection-locked oscillator (ILO) based input clock-and-data recovery (CDR) unit cascaded with a jitter filter phase-locked loop (PLL) that generates low-jitter clocks for the output transmitter that serializes and retimes the recovered data. The input ILO-based CDR employs a quarter-rate architecture for efficient wide-range operation and utilizes a digital loop filter with pattern filtering for robust input delay line and ILO frequency control. Fabricated in 28 nm CMOS, the proposed retimer operates from 12−20 Gb/s, achieves the widest-reported 20 Gb/s jitter tolerance (JTOL) of 1UIPP at a 173 MHz sinusoidal jitter (SJ) frequency and an estimated JTOL bandwidth in excess of 500 MHz, and consumes 58.66 mW.