Energy-efficient Ising solver implementations in forming-free memristor crossbar arrays for combinatorial optimization problems

Abstract

The core approach of Ising solvers for combinatorial optimization problems is the simulated annealing (SA) algorithm. Although hardware-based SA methods have been explored in electronic, optical, and quantum systems, studies that explicitly consider the conductance range and noise characteristics of memory devices remain limited. Here, we present a weight-profile design strategy for an SA-based Hopfield neural network implemented in a 32 × 32 memristor crossbar array. By optimizing the post-deposition annealing process, forming-free operation with 100 % yield and full programmability across the array is achieved. Noise analysis shows that lower conductance states and reduced read voltages induce stronger random fluctuations, which can be exploited as intrinsic noise sources. Using this property, the 32-node max-cut problem was experimentally solved by mapping subdivided conductance ranges and dynamically modulating the read voltage. Higher resistance states provided sufficient entropy to enhance SA operations, thereby improving convergence and reducing power consumption. This work demonstrates that intrinsic device noise, when combined with optimized weight-profile design, can minimize hardware overhead while significantly boosting energy efficiency and overall system performance.