Enhancement Mechanisms of the Silicon-Oxide-Nitride-Oxide-Silicon Memory Devices with Nanoscale High-k Structures

Abstract

The electrical properties of silicon-oxide-nitride-oxide-siliconmemory devices with nanoscale high-k structures in the charge trap layer were investigated. Simulation results showed that both the amount of trap charge injected in the nitride layer and the retention characteristics were improved by employing suitable high-k structures. The threshold voltage shift of the optimized device was increased by 9% from the conventional device without high-k structures. The enhancement mechanisms for the electrical characteristics can be explained in terms of the vertical electric field in the charge trap layer and the tunneling oxide layer.