Design and Analysis of Efficient Parallel Hardware Prime Generators
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, Dong Kyue | - |
dc.contributor.author | Choi, Piljoo | - |
dc.contributor.author | Lee, Mun-Kyu | - |
dc.contributor.author | Park, Heejin | - |
dc.date.accessioned | 2021-08-02T16:27:06Z | - |
dc.date.available | 2021-08-02T16:27:06Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2016-10 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/22145 | - |
dc.description.abstract | We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Design and Analysis of Efficient Parallel Hardware Prime Generators | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Dong Kyue | - |
dc.contributor.affiliatedAuthor | Park, Heejin | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.5.564 | - |
dc.identifier.scopusid | 2-s2.0-84994320326 | - |
dc.identifier.wosid | 000393191000006 | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.5, pp.564 - 581 | - |
dc.relation.isPartOf | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 16 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 564 | - |
dc.citation.endPage | 581 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordPlus | PRIMALITY | - |
dc.subject.keywordPlus | EXPONENTIATION | - |
dc.subject.keywordPlus | TESTS | - |
dc.subject.keywordAuthor | Performance analysis | - |
dc.subject.keywordAuthor | digital integrated circuits | - |
dc.subject.keywordAuthor | prime number | - |
dc.subject.keywordAuthor | public key cryptosystem | - |
dc.subject.keywordAuthor | information security | - |
dc.identifier.url | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07041139&language=ko_KR&hasTopBanner=true | - |
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