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Design and Analysis of Efficient Parallel Hardware Prime Generators

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dc.contributor.authorKim, Dong Kyue-
dc.contributor.authorChoi, Piljoo-
dc.contributor.authorLee, Mun-Kyu-
dc.contributor.authorPark, Heejin-
dc.date.accessioned2021-08-02T16:27:06Z-
dc.date.available2021-08-02T16:27:06Z-
dc.date.created2021-05-12-
dc.date.issued2016-10-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/22145-
dc.description.abstractWe present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.-
dc.language영어-
dc.language.isoen-
dc.publisherIEEK PUBLICATION CENTER-
dc.titleDesign and Analysis of Efficient Parallel Hardware Prime Generators-
dc.typeArticle-
dc.contributor.affiliatedAuthorKim, Dong Kyue-
dc.contributor.affiliatedAuthorPark, Heejin-
dc.identifier.doi10.5573/JSTS.2016.16.5.564-
dc.identifier.scopusid2-s2.0-84994320326-
dc.identifier.wosid000393191000006-
dc.identifier.bibliographicCitationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.5, pp.564 - 581-
dc.relation.isPartOfJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.titleJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.citation.volume16-
dc.citation.number5-
dc.citation.startPage564-
dc.citation.endPage581-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.isOpenAccessN-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.description.journalRegisteredClasskci-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaPhysics-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryPhysics, Applied-
dc.subject.keywordPlusPRIMALITY-
dc.subject.keywordPlusEXPONENTIATION-
dc.subject.keywordPlusTESTS-
dc.subject.keywordAuthorPerformance analysis-
dc.subject.keywordAuthordigital integrated circuits-
dc.subject.keywordAuthorprime number-
dc.subject.keywordAuthorpublic key cryptosystem-
dc.subject.keywordAuthorinformation security-
dc.identifier.urlhttps://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE07041139&language=ko_KR&hasTopBanner=true-
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서울 공과대학 > 서울 컴퓨터소프트웨어학부 > 1. Journal Articles
서울 공과대학 > 서울 융합전자공학부 > 1. Journal Articles

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