Design and Analysis of Efficient Parallel Hardware Prime Generators
- Authors
- Kim, Dong Kyue; Choi, Piljoo; Lee, Mun-Kyu; Park, Heejin
- Issue Date
- Oct-2016
- Publisher
- IEEK PUBLICATION CENTER
- Keywords
- Performance analysis; digital integrated circuits; prime number; public key cryptosystem; information security
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.16, no.5, pp.564 - 581
- Indexed
- SCIE
SCOPUS
KCI
- Journal Title
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
- Volume
- 16
- Number
- 5
- Start Page
- 564
- End Page
- 581
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/22145
- DOI
- 10.5573/JSTS.2016.16.5.564
- ISSN
- 1598-1657
- Abstract
- We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.
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