Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
DC Field | Value | Language |
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dc.contributor.author | Han, Jae duk | - |
dc.contributor.author | Lu, Yue | - |
dc.contributor.author | Sutardja, Nicholas | - |
dc.contributor.author | Jung, Kwangmo | - |
dc.contributor.author | Alon, Elad | - |
dc.date.accessioned | 2021-08-02T16:54:41Z | - |
dc.date.available | 2021-08-02T16:54:41Z | - |
dc.date.created | 2021-05-14 | - |
dc.date.issued | 2016-04 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/23184 | - |
dc.description.abstract | Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals-this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Han, Jae duk | - |
dc.identifier.doi | 10.1109/JSSC.2016.2519389 | - |
dc.identifier.scopusid | 2-s2.0-84978017174 | - |
dc.identifier.wosid | 000374404300009 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.4, pp.871 - 880 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 51 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 871 | - |
dc.citation.endPage | 880 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DECISION-FEEDBACK EQUALIZER | - |
dc.subject.keywordPlus | I/O | - |
dc.subject.keywordPlus | LINK | - |
dc.subject.keywordAuthor | Chip-to-chip communication | - |
dc.subject.keywordAuthor | current integration | - |
dc.subject.keywordAuthor | decision feedback equalizer (DFE) | - |
dc.subject.keywordAuthor | feedforward equalizer (FFE) | - |
dc.subject.keywordAuthor | high-speed links | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/7437437 | - |
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