Reliability Degeneration Mechanisms of the 20-nm Flash Memories Due to the Word Line Stress
- Authors
- Jung, Hyun Soo; Ryu, Ju Tae; Yoo, Keon-Ho; Kim, Tae Whan
- Issue Date
- Feb-2016
- Publisher
- AMER SCIENTIFIC PUBLISHERS
- Keywords
- NAND Flash Memory; Word Line Stress; Degeneration Mechanism; Program/Erase Cycle
- Citation
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v.16, no.2, pp.1669 - 1671
- Indexed
- SCIE
SCOPUS
- Journal Title
- JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY
- Volume
- 16
- Number
- 2
- Start Page
- 1669
- End Page
- 1671
- URI
- https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/24014
- DOI
- 10.1166/jnn.2016.11950
- ISSN
- 1533-4880
- Abstract
- The electrical characteristics of NAND flash memories with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The occurrence rate of the errors in the flash memories increases with increasing program/erase cycles. To verify the word line stress effect, electron density in the floating gate of target cell and non-target cell, the drain current in the channel of non-target cell and depletion region of the non-target cell were simulated as a function of program/erase cycle, for various floating gate thicknesses. The electron density in the floating gate became decreased with increasing program/erase cycles. The reliability degradation occured by the increased depletion region at the bottom of the polysilicon floating gate in the continued program/erase cycle situation due to the word line stress. The degradation mechanisms for the program characteristics of 20-nm NAND flash memories were clarified by examining electron density, darin current and depletion region.
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