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Improved Electrical Chararcteristics of Gate-Last FD-SOI TFETs with All ALD High-K/Metal Gate Stack Using D2 Passivation
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | 최창환 | - |
| dc.date.accessioned | 2021-08-03T03:52:39Z | - |
| dc.date.available | 2021-08-03T03:52:39Z | - |
| dc.date.issued | 2017-04-03 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/33481 | - |
| dc.title | Improved Electrical Chararcteristics of Gate-Last FD-SOI TFETs with All ALD High-K/Metal Gate Stack Using D2 Passivation | - |
| dc.type | Conference | - |
| dc.citation.conferenceName | International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon | - |
| dc.citation.conferencePlace | 아테네/그리스 | - |
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Collections - 서울 공과대학 > 서울 신소재공학부 > 2. Conference Papers
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Related Researcher
- Choi, Chang hwan
- COLLEGE OF ENGINEERING (SCHOOL OF MATERIALS SCIENCE AND ENGINEERING)