Design Techniques for Robust and Area-efficient Current Sources in Nanometer CMOS Technology

Abstract

In advanced CMOS technology nodes, stacked short-channel transistors are favored over long-channel transistors for constructing current sources, as they are less constrained by design rules that require additional spacing and transition area for mixing transistors with different channel lengths. In this work, we propose various metrics such as current density (\mathbf{I}{\mathbf{D}}/\mathbf{W}), normalized output impedance (\mathbf{r}{\mathbf{o}}\mathbf{I}{\mathbf{D}}), current normalized to top transistor width (\mathbf{I}{\mathbf{D}}/ \mathbf{W}{\mathbf{top}}), to quantify the performance and resource consumptions of current sources across various device stacks and width ratios. The exploration results reveal that the stacked current source achieve lower area consumption and less parasitic capacitance if the top transistor width is scaled up properly, rather than simply stacking uniform transistors.