Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
DC Field | Value | Language |
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dc.contributor.author | Han, Jae duk | - |
dc.contributor.author | Sutardja, Nicholas | - |
dc.contributor.author | Lu, Yue | - |
dc.contributor.author | Alon, Elad | - |
dc.date.accessioned | 2021-07-30T05:17:11Z | - |
dc.date.available | 2021-07-30T05:17:11Z | - |
dc.date.created | 2021-05-14 | - |
dc.date.issued | 2017-12 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/3950 | - |
dc.description.abstract | Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Han, Jae duk | - |
dc.identifier.doi | 10.1109/JSSC.2017.2740268 | - |
dc.identifier.scopusid | 2-s2.0-85029178192 | - |
dc.identifier.wosid | 000417192200027 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.52, no.12, pp.3474 - 3485 | - |
dc.relation.isPartOf | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 52 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 3474 | - |
dc.citation.endPage | 3485 | - |
dc.type.rims | ART | - |
dc.type.docType | 정기학술지(Article(Perspective Article포함)) | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | DECISION-FEEDBACK EQUALIZER | - |
dc.subject.keywordPlus | 65 NM CMOS | - |
dc.subject.keywordPlus | SERIAL LINK | - |
dc.subject.keywordPlus | GB/S | - |
dc.subject.keywordPlus | I/O | - |
dc.subject.keywordPlus | FFE | - |
dc.subject.keywordAuthor | Chip-to-chip communication | - |
dc.subject.keywordAuthor | clock and data recovery (CDR) | - |
dc.subject.keywordAuthor | current integration | - |
dc.subject.keywordAuthor | decision feedback equalizer (DFE) | - |
dc.subject.keywordAuthor | feed-forward equalizer (FFE) | - |
dc.subject.keywordAuthor | high-speed links | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8025518 | - |
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