Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector
DC Field | Value | Language |
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dc.contributor.author | Song, Seung-Hyun | - |
dc.contributor.author | Kim, Min-Won | - |
dc.contributor.author | Yoo, Sang-Dong | - |
dc.contributor.author | Shim, Tae-Hun | - |
dc.contributor.author | Park, Jea-Gun | - |
dc.date.accessioned | 2021-07-30T05:31:38Z | - |
dc.date.available | 2021-07-30T05:31:38Z | - |
dc.date.created | 2021-05-12 | - |
dc.date.issued | 2018-07 | - |
dc.identifier.issn | 0003-6951 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/5285 | - |
dc.description.abstract | We proposed a two-terminal-electrode vertical thyristor and investigated its suitability as a cross point memory cell without a selector from the viewpoints of p(+)- and n(+)-base region width and a vertically stacked doped-epitaxial-Si layer structure such as p(++)-emitter/n(+)-base/p(+)-base/n(++)-emitter or n(++)-emitter/p(+)-base/n(+)-base/p(++)-emitter. The proper p(+)- and n(+)-base-region width (i.e., 160 nm) and p(++)emitter/n(+)-base/p(+)-base/n(++)-emitter layer structure could enable the development of a cross-point memory cell using the half bias concept by preventing misfit dislocations at the junctions between the n(++)-emitter and p(+)-base or n(+)-base and p(++)-emitter. It was also found that generation of the misfit dislocations originating from B or P atom segregation at junctions during doped-Si epitaxial-layer growth enhanced the strain at the junctions. The misfit dislocations at the junctions were produced when the strain at the junctions was greater than similar to 4 x 10(-4). | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | AMER INST PHYSICS | - |
dc.title | Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Park, Jea-Gun | - |
dc.identifier.doi | 10.1063/1.5040426 | - |
dc.identifier.scopusid | 2-s2.0-85051111892 | - |
dc.identifier.wosid | 000440813000014 | - |
dc.identifier.bibliographicCitation | APPLIED PHYSICS LETTERS, v.113, no.5 | - |
dc.relation.isPartOf | APPLIED PHYSICS LETTERS | - |
dc.citation.title | APPLIED PHYSICS LETTERS | - |
dc.citation.volume | 113 | - |
dc.citation.number | 5 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Physics | - |
dc.relation.journalWebOfScienceCategory | Applied | - |
dc.identifier.url | https://pubs.aip.org/aip/apl/article/113/5/052103/36472/Design-of-two-terminal-electrode-vertical | - |
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