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8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Choi, M. | - |
| dc.contributor.author | Wang, Z. | - |
| dc.contributor.author | Lee, K. | - |
| dc.contributor.author | Park, K. | - |
| dc.contributor.author | Liu, Z. | - |
| dc.contributor.author | Biswas, A. | - |
| dc.contributor.author | Han, J. | - |
| dc.contributor.author | Alon, E. | - |
| dc.date.accessioned | 2021-07-30T08:10:15Z | - |
| dc.date.available | 2021-07-30T08:10:15Z | - |
| dc.date.created | 2021-07-19 | - |
| dc.date.issued | 2021-02-13 | - |
| dc.identifier.issn | 0193-6530 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hanyang/handle/2021.sw.hanyang/6233 | - |
| dc.description.abstract | The ever-expanding demand for ultra-high-speed interconnects has driven the development of wireline TXs operating at >100Gb/s per lane [1]-[4]. This paper presents a PAM-4 TX achieving 200Gb/s with improved output bandwidth and output swing by minimizing the driver capacitance with pull-up current sources, multiplexing with flexible clock timing control, and employing a fully reconfigurable 5-tap FFE architecture. © 2021 IEEE. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | 8 An Output-Bandwidth-Optimized 200Gb/s PAM-4 100Gb/s NRZ Transmitter with 5-Tap FFE in 28nm CMOS | - |
| dc.type | Conference | - |
| dc.contributor.affiliatedAuthor | Han, J. | - |
| dc.identifier.scopusid | 2-s2.0-85102371344 | - |
| dc.identifier.bibliographicCitation | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021, pp.128 - 130 | - |
| dc.relation.isPartOf | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 | - |
| dc.relation.isPartOf | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | - |
| dc.citation.title | 2021 IEEE International Solid-State Circuits Conference, ISSCC 2021 | - |
| dc.citation.startPage | 128 | - |
| dc.citation.endPage | 130 | - |
| dc.citation.conferencePlace | US | - |
| dc.citation.conferenceDate | 2021-02-13 | - |
| dc.type.rims | CONF | - |
| dc.description.journalClass | 1 | - |
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Related Researcher
- Han, Jaeduk
- COLLEGE OF ENGINEERING (SCHOOL OF ELECTRONIC ENGINEERING)