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Error Rate-Based Log-Likelihood Ratio Processing for Low-Density Parity-Check Codes in DNA Storage

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dc.contributor.authorLu, Xiaozhou-
dc.contributor.authorJeong, Jaeho-
dc.contributor.authorKim, Jae-Won-
dc.contributor.authorNo, Jong-Seon-
dc.contributor.authorPark, Hosung-
dc.contributor.authorNo, Albert-
dc.contributor.authorKim, Sunghwan-
dc.date.available2021-03-17T06:50:32Z-
dc.date.created2021-02-26-
dc.date.issued2020-09-
dc.identifier.issn2169-3536-
dc.identifier.urihttps://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/11588-
dc.description.abstractDue to the advantages of high storage densities and longevity, DNA storage has become one of the attractive technologies for future data storage systems. However, the writing/reading cost is still high and more efficient techniques for DNA storage are required. In this paper, we propose improved log-likelihood ratio (LLR) processing schemes based on observed statistics for low-density parity-check (LDPC) code decoding to reduce reading cost while encoding schemes are kept unchanged. Due to the mismatch between the real channel and the observed statistics and also the limit of maximum decoder input value, scaling the magnitude of LLR can lead to a better error correcting performance. Therefore, we propose two strategies: 1) directly scaling LLRs and 2) scaling pairwise substitution error rates, which changes the magnitude of LLRs. We also suggest the relation between substitution error rate and scaling values in the strategies by using curve fitting methods. Simulation results show that the error correcting performance from the proposed LLR calculation is better than that from the conventional scheme. Finally, we verify that the proposed LLR methods can be generally applied in DNA storage systems, and present practical methods to calculate error rates.-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleError Rate-Based Log-Likelihood Ratio Processing for Low-Density Parity-Check Codes in DNA Storage-
dc.typeArticle-
dc.contributor.affiliatedAuthorNo, Albert-
dc.identifier.doi10.1109/ACCESS.2020.3021700-
dc.identifier.scopusid2-s2.0-85102673044-
dc.identifier.wosid000573013300001-
dc.identifier.bibliographicCitationIEEE ACCESS, v.8, pp.162892 - 162902-
dc.relation.isPartOfIEEE ACCESS-
dc.citation.titleIEEE ACCESS-
dc.citation.volume8-
dc.citation.startPage162892-
dc.citation.endPage162902-
dc.type.rimsART-
dc.type.docTypeArticle-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.relation.journalResearchAreaComputer Science-
dc.relation.journalResearchAreaEngineering-
dc.relation.journalResearchAreaTelecommunications-
dc.relation.journalWebOfScienceCategoryComputer Science, Information Systems-
dc.relation.journalWebOfScienceCategoryEngineering, Electrical & Electronic-
dc.relation.journalWebOfScienceCategoryTelecommunications-
dc.subject.keywordAuthorDNA-
dc.subject.keywordAuthorParity check codes-
dc.subject.keywordAuthorError analysis-
dc.subject.keywordAuthorDecoding-
dc.subject.keywordAuthorChannel models-
dc.subject.keywordAuthorEncoding-
dc.subject.keywordAuthorSimulation-
dc.subject.keywordAuthorDNA storage-
dc.subject.keywordAuthorerror correction codes-
dc.subject.keywordAuthorlow-density parity-check (LDPC) codes-
dc.subject.keywordAuthorlog-likelihood ratio (LLR)-
dc.subject.keywordAuthorerror rate-
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