Line-edge roughness on fin-field-effect-Transistor performance for below 10nm patterns

Abstract

As the critical dimension (CD) of electronic devices continues to be scaled down to less than 10-nm in size, the line-edge roughness (LER) becomes a critical issue that significantly affects the CD, as well as the device performance because the LER does not scale along with the feature size. Therefore, the LER needs to be reduced to continue to shrink the feature size as well as minimize the device malfunctions. In this study, the LER impacts on the performance of fin-field-effect-transistors (FinFETs) are investigated using a compact device method. For the fluctuation of electric potentials due to the fin-width roughness (FWR) based on the stochastic fluctuation during the lithography process, electric potentials with fat-fin, thin-fin, big-source, and big-drain FWRs are right shift, left shift, down shift, and upper shift to the electric potential without FWR, respectively. For the fluctuation of drain currents due to gate voltages, drain currents with fat-fin, big-source, and big-drain FWRs are righter shift in order. According to the Taguchi method, gate voltage and channel length are more dominant parameters on the sensitivity of electronic potential and current drain of a FinFET device.