Regularities Considered Harmful: Forcing Randomness to Memory Accesses to Reduce Row Buffer Conflicts for Multi-Core, Multi-Bank Systems
- Authors
- Park, Heekwon; Baek, Seungjae; Choi, Jongmoo; Lee, Donghee; Noh, Sam H.
- Issue Date
- Apr-2013
- Publisher
- ASSOC COMPUTING MACHINERY
- Keywords
- Algorithms; Design; Experimentation; Measurement; Performance; Row-buffer conflict; Memory management; Randomized algorithm; Memory container; Analysis tool
- Citation
- ACM SIGPLAN NOTICES, v.48, no.4, pp.181 - 191
- Journal Title
- ACM SIGPLAN NOTICES
- Volume
- 48
- Number
- 4
- Start Page
- 181
- End Page
- 191
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/17159
- DOI
- 10.1145/2499368.2451137
- ISSN
- 0362-1340
- Abstract
- We propose a novel kernel-level memory allocator, called M-3 (M-cube, Multi-core Multi-bank Memory allocator), that has the following two features. First, it introduces and makes use of a notion of a memory container, which is defined as a unit of memory that comprises the minimum number of page frames that can cover all the banks of the memory organization, by exclusively assigning a container to a core so that each core achieves bank parallelism as much as possible. Second, it orchestrates page frame allocation so that pages that threads access are dispersed randomly across multiple banks so that each thread's access pattern is randomized. The development of M-3 is based on a tool that we develop to fully understand the architectural characteristics of the underlying memory organization. Using an extension of this tool, we observe that the same application that accesses pages in a random manner outperforms one that accesses pages in a regular pattern such as sequential or same ordered accesses. This is because such randomized accesses reduces inter-thread access interference on the rowbuffer in memory banks. We implement M-3 in the Linux kernel version 2.6.32 on the Intel Xeon system that has 16 cores and 32GB DRAM. Performance evaluation with various workloads show that M-3 improves the overall performance for memory intensive benchmarks by up to 85% with an average of about 40%.
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- Appears in
Collections - College of Engineering > Computer Engineering Major > 1. Journal Articles
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