A 0.1-1.5 GHz all-digital phase inversion delay-locked loop
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, S. | - |
dc.contributor.author | Kim, T. | - |
dc.contributor.author | Kim, J. | - |
dc.date.accessioned | 2021-11-11T04:44:13Z | - |
dc.date.available | 2021-11-11T04:44:13Z | - |
dc.date.created | 2021-11-10 | - |
dc.date.issued | 2013 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/17327 | - |
dc.description.abstract | An all-digital, wide-range phase inversion delay-locked loop (PIDLL) with a high-resolution duty-cycle corrector (DCC) is presented. The proposed PIDLL utilizes a new phase inversion scheme to reduce the total number of delay elements (DEs) in the digitally controlled delay line (DCDL) by approximately one-half, enabling shorter locking times, lower power consumption, reduced jitter performance, and a smaller area, while maintaining a wide operating frequency range. To achieve high delay resolution and linear delay characteristics, a three-stage DCDL using a new area-efficient digital feedback delay element (FDE) is proposed. The FDE is also utilized to implement a new DCC that obtains a duty-cycle error of less than ±0.85% over a 30-70% input duty-cycle range. The proposed DCC-equipped PIDLL is implemented in a 0.13-μm CMOS process, occupies an area of 0.11 mm2, and operates over a wide frequency range of 0.1-1.5 GHz. It dissipates power of 5.9 mW from a 1.2 V supply at 1 GHz and exhibits a peak-to-peak output clock jitter of 11.25 ps at 1.5 GHz. © 2013 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.subject | Delay characteristics | - |
dc.subject | Delay-locked loops | - |
dc.subject | Digital feedback | - |
dc.subject | Digitally controlled | - |
dc.subject | Jitter performance | - |
dc.subject | Lower-power consumption | - |
dc.subject | Operating frequency | - |
dc.subject | Wide frequency range | - |
dc.subject | CMOS integrated circuits | - |
dc.subject | Locks (fasteners) | - |
dc.title | A 0.1-1.5 GHz all-digital phase inversion delay-locked loop | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, J. | - |
dc.identifier.doi | 10.1109/ASSCC.2013.6691052 | - |
dc.identifier.scopusid | 2-s2.0-84893592522 | - |
dc.identifier.bibliographicCitation | Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013, pp.341 - 344 | - |
dc.relation.isPartOf | Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 | - |
dc.citation.title | Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 | - |
dc.citation.startPage | 341 | - |
dc.citation.endPage | 344 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordPlus | Delay characteristics | - |
dc.subject.keywordPlus | Delay-locked loops | - |
dc.subject.keywordPlus | Digital feedback | - |
dc.subject.keywordPlus | Digitally controlled | - |
dc.subject.keywordPlus | Jitter performance | - |
dc.subject.keywordPlus | Lower-power consumption | - |
dc.subject.keywordPlus | Operating frequency | - |
dc.subject.keywordPlus | Wide frequency range | - |
dc.subject.keywordPlus | CMOS integrated circuits | - |
dc.subject.keywordPlus | Locks (fasteners) | - |
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