A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Han, S. | - |
dc.contributor.author | Kim, J. | - |
dc.date.accessioned | 2021-12-02T04:45:34Z | - |
dc.date.available | 2021-12-02T04:45:34Z | - |
dc.date.created | 2021-11-30 | - |
dc.date.issued | 2012 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/19111 | - |
dc.description.abstract | This paper presents a dual-loop digital delay-locked loop (DLL) for high-speed DRAM applications. The dual-loop architecture using a hybrid (binary + sequential) search algorithm is proposed to achieve both wide-range operation and high delay resolution while maintaining the closed-loop property that allows for tracking of PVT variations. A new phaseinterpolation range selector (PIRS) and a variable successive approximation register (VSAR) algorithm are adopted to resolve the boundary switching and harmonic locking problems of conventional digital DLLs. The proposed digital DLL, implemented in a 0.18-μm CMOS process, occupies an active area of only 0.19mm2 and operates over a wide frequency range of 0.15-1.5 GHz. The DLL also dissipates a power of 11.3 mW from a 1.8 V supply at 1 GHz. The measured peak-to-peak output clock jitter is 24 ps with an input clock jitter of 7.5 ps at 1.5 GHz. The delay resolution is only 2.2 ps. © 2012 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.title | A high-resolution wide-range dual-loop digital delay-locked loop using a hybrid search algorithm | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, J. | - |
dc.identifier.doi | 10.1109/IPEC.2012.6522683 | - |
dc.identifier.scopusid | 2-s2.0-84881046965 | - |
dc.identifier.bibliographicCitation | Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.293 - 296 | - |
dc.relation.isPartOf | Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC | - |
dc.citation.title | Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC | - |
dc.citation.startPage | 293 | - |
dc.citation.endPage | 296 | - |
dc.type.rims | ART | - |
dc.type.docType | Conference Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
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