Multi-Stage Decoding Scheme with Post-Processing for LDPC Codes to Lower the Error Floors
- Authors
- Shin, Beomkyu; Park, Hosung; No, Jong-Seon; Chung, Habong
- Issue Date
- Aug-2011
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- error floor; log-likelihood ratio (LLR); low-density parity-check (LDPC) codes; sum-product algorithm
- Citation
- IEICE TRANSACTIONS ON COMMUNICATIONS, v.E94B, no.8, pp.2375 - 2377
- Journal Title
- IEICE TRANSACTIONS ON COMMUNICATIONS
- Volume
- E94B
- Number
- 8
- Start Page
- 2375
- End Page
- 2377
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/19830
- DOI
- 10.1587/transcom.E94.B.2375
- ISSN
- 0916-8516
- Abstract
- In this letter, we propose a multi-stage decoding scheme with post-processing for low-density parity-check (LDPC) codes, which remedies the rapid performance degradation in the high signal-to-noise ratio (SNR) range known as error floor. In the proposed scheme, the unsuccessfully decoded words of the previous decoding stage are re-decoded by manipulating the received log-likelihood ratios (LLRs) of the properly selected variable nodes. Two effective criteria for selecting the probably erroneous variable nodes are also presented. Numerical results show that the proposed scheme can correct most of the unsuccessfully decoded words of the first stage having oscillatory behavior, which are regarded as a main cause of the error floor.
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Collections - College of Engineering > School of Electronic & Electrical Engineering > 1. Journal Articles
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