Formation of through-silicon-vias using Sn filling process for 3D packaging

Abstract

Through-silicon-vias were formed with Sn filling process and their characteristics were evaluated to form three-dimensional-interconnection structure of chip stack packages. Contrary to the conventional Cu vias which require complicate and long Cu electroplating, Sn vias could be formed easily by Sn electroplating and reflow. Sn via-filling behavior did not depend on the shape of the Sn electroplated layer, allowing much wider process window for Sn via formation compared to the conventional Cu via process. Interlocking-joint structure was formed by inserting Cu bumps of 20 μm diameter into Sn vias of 50 μm diameter at 250°C for 2 min. Melt-joint structure was formed by reflowing Sn bumps of 55 μm diameter on Sn vias of 50 μm diameter at 250°C for 2 min. Both interlocking-joint structure and melt-joint structure exhibited high chip-shear-forces of 50 N and 30 ∼40N, respectively. Comparing microstructures of the interlocking-joint structure and the melt-joint structure with the conventional planar Cu via/bump interface, it is expected that much higher mechanical reliability can be obtained for the interlocking-joint structure and the melt-joint structure formed on Sn vias.