Electrical characteristics of the three-dimensional interconnection structure for the chip stack package with Cu through vias
DC Field | Value | Language |
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dc.contributor.author | Lee, Kwang-Yong | - |
dc.contributor.author | Oh, Teck-Su | - |
dc.contributor.author | lee, Jae-Ho | - |
dc.contributor.author | Oh, Tae-Sung | - |
dc.date.accessioned | 2022-01-14T07:43:38Z | - |
dc.date.available | 2022-01-14T07:43:38Z | - |
dc.date.created | 2022-01-14 | - |
dc.date.issued | 2007-02 | - |
dc.identifier.issn | 0361-5235 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/23641 | - |
dc.description.abstract | A chip stack specimen of a three-dimensional (3-D) interconnection structure with Cu vias of 75-mu m diameter, 90-mu m height, and 150-mu m pitch was successfully fabricated using via hole formation with deep reactive ion etching (RIE), Cu via filling with pulse-reverse pulse electroplating, Si thinning, Cull Sn bump formation, and flip-chip bonding. The contact resistance of a Cu/Sn bump joint and Cu via resistance could be determined from the slope of the daisy chain resistance versus the number of bump joints of the flip-chip specimen containing Cu vias. When the flip chip was bonded at 270 degrees C for 2 min, the contact resistance of a Cu/Sn bump joint of 100-mu m diameter was 6.74 m Omega, and the resistance of a Cu via of 75-mu m diameter and 90-mu m height was 2.31 m Omega. As the power transmission characteristics of the Cu through via, the S-21 parameter was measured up to 20 GHz. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | SPRINGER | - |
dc.title | Electrical characteristics of the three-dimensional interconnection structure for the chip stack package with Cu through vias | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | lee, Jae-Ho | - |
dc.contributor.affiliatedAuthor | Oh, Tae-Sung | - |
dc.identifier.doi | 10.1007/s11664-006-0020-5 | - |
dc.identifier.scopusid | 2-s2.0-33947594905 | - |
dc.identifier.wosid | 000244727800005 | - |
dc.identifier.bibliographicCitation | JOURNAL OF ELECTRONIC MATERIALS, v.36, no.2, pp.123 - 128 | - |
dc.relation.isPartOf | JOURNAL OF ELECTRONIC MATERIALS | - |
dc.citation.title | JOURNAL OF ELECTRONIC MATERIALS | - |
dc.citation.volume | 36 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 123 | - |
dc.citation.endPage | 128 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Materials Science | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Materials Science, Multidisciplinary | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | chip stack package | - |
dc.subject.keywordAuthor | system in package | - |
dc.subject.keywordAuthor | Cu via | - |
dc.subject.keywordAuthor | electroplating | - |
dc.subject.keywordAuthor | interconnection | - |
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