Development and evaluation of 3-D SiP with vertically interconnected Through Silicon Vias (TSV)
- Authors
- Jang, D.M.; Ryu, C.; Lee, K.Y.; Cho, B.H.; Kim, J.; Oh, T.S.; Lee, W.J.; Yu, J.
- Issue Date
- 2007
- Citation
- Proceedings - Electronic Components and Technology Conference, pp.847 - 852
- Journal Title
- Proceedings - Electronic Components and Technology Conference
- Start Page
- 847
- End Page
- 852
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/24245
- DOI
- 10.1109/ECTC.2007.373897
- ISSN
- 0569-5503
- Abstract
- For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of stacked chip type 3-D SiP with vertically interconnected TSV are reported. The process includes; 55μm-diameter via holes by reactive ion etching (RIE), SiO2 dielectric layer by thermal oxidation, Ta and Cu seed layers by ionized metal plasma (IMP), Cu via filling by electroplating, Cu/Sn bump for multi-chip stacking and finally chip-to-PCB bonding with Sn-3.0Ag-0.5Cu solder and ENIG pad. A prototype 3-D SiP with 10 stacked chips was successfully fabricated. High frequency electrical model of the TSV was proposed and the model parameters were extracted from the measured S-parameters. The proposed model was verified by TDR/TDT (time domain reflectometry/time domain transmission) and eye-diagram measurement. And then, contact resistances of Cu via and bump joint were discussed. ©2007 IEEE.
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Collections - College of Engineering > Materials Science and Engineering Major > 1. Journal Articles
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