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Atomic layer deposition of Al2O3/NiO/Al 2O3 laminate structures for nonvolatile memory device applications

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dc.contributor.authorCho, W.-
dc.contributor.authorYou, Y.-H.-
dc.contributor.authorLee, S.S.-
dc.contributor.authorChung, T.-M.-
dc.contributor.authorLee, Y.K.-
dc.contributor.authorKim, C.G.-
dc.contributor.authorHwang, J.-H.-
dc.contributor.authorAn, K.-S.-
dc.date.accessioned2022-02-07T07:42:30Z-
dc.date.available2022-02-07T07:42:30Z-
dc.date.created2022-02-07-
dc.date.issued2006-
dc.identifier.issn1938-5862-
dc.identifier.urihttps://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/25043-
dc.description.abstractWe have fabricated Al2O3/NiO/Al2O 3 nano-laminate structures on Si(001) substrate using atomic layer deposition (ALD) technique for floating gate memory application. The nonvolatile capacitance-voltage (C-V) characterisitics have been investigated. NiO and Al2O3 films, as charge trapping and insulating barrier layer, were deposited using newly-synthesized Ni aminoalkoxide (Ni(dmamb) 2) and trimethylaluminum (TMA) with H2O, respectively. The hysteresis voltage window of the Al2O3 (20nm)/NiO (5 nm)/Al2O3 (5 nm) laminate structure is ∼8.6 V in voltage sweep range from -7.5 to 7.5 V, while there is no hysteresis in the Al2O3 film. copyright The Electrochemical Society.-
dc.language영어-
dc.language.isoen-
dc.publisherElectrochemical Society Inc.-
dc.titleAtomic layer deposition of Al2O3/NiO/Al 2O3 laminate structures for nonvolatile memory device applications-
dc.typeArticle-
dc.contributor.affiliatedAuthorHwang, J.-H.-
dc.identifier.doi10.1149/1.2721498-
dc.identifier.scopusid2-s2.0-45749090123-
dc.identifier.bibliographicCitationECS Transactions, v.3, no.15, pp.283 - 285-
dc.relation.isPartOfECS Transactions-
dc.citation.titleECS Transactions-
dc.citation.volume3-
dc.citation.number15-
dc.citation.startPage283-
dc.citation.endPage285-
dc.type.rimsART-
dc.type.docTypeConference Paper-
dc.description.journalClass1-
dc.description.journalRegisteredClassscopus-
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