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Fabrication and characterization of three dimensional interconnection structures for system in packages
- Authors
- Lee, K.-Y.; Oh, T.-S.
- Issue Date
- 2006
- Keywords
- Chip stack package; Cu via; Electroplating; Interconnection; System in package
- Citation
- Proceedings - 2006 International Symposium on Microelectronics, IMAPS 2006, pp.1378 - 1382
- Journal Title
- Proceedings - 2006 International Symposium on Microelectronics, IMAPS 2006
- Start Page
- 1378
- End Page
- 1382
- ISSN
- 0000-0000
- Abstract
- Three-dimensional interconnection structure for chip stack package was processed with Cu via filling and bump formation by electrodeposition. Cu filling behavior and average resistance of a 3D interconnection joint composed of a Cu via and Cu/Sn bump bonding were investigated. To facilitate the observation for Cu via filling behavior, trench vias of75~10 A® width were fabricated and filled by Cu electroplating with variations of electroplating current density and current mode. Cu/Sn bumps were fabricated under Cu vias and bonded to Cu/Sn bumps of the substrate for' chip stack process. Micros true tare and electrical properties of the 3D interconnection joint were characterized. When flip-chip bonded at 270 V for 2 minutes, the resistance of a 3D interconnection joint composed of a Cu via and Cu/Sn bump bonding was evaluated as 13.1 mQ. Copyright © 2006 IMAPS.
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