Characterization of High-Performance InGaAs QW-MOSFETs With Reliable Bi-Layer HfOxNy Gate Stack
DC Field | Value | Language |
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dc.contributor.author | Eom, Su-Keun | - |
dc.contributor.author | Kong, Min-Woo | - |
dc.contributor.author | Cha, Ho-Young | - |
dc.contributor.author | Seo, Kwang-Seok | - |
dc.date.available | 2020-07-10T04:14:19Z | - |
dc.date.created | 2020-07-06 | - |
dc.date.issued | 2019 | - |
dc.identifier.issn | 2168-6734 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/2772 | - |
dc.description.abstract | In this work, we report high-performance InGaAs quantum-well MOSFETs with optimized bi-layer high-k gate dielectrics incorporating high-quality plasma-assisted atomic -layer-deposited (PA-ALD) HfOxNy interfacial layer (IL). With more than 1 nm IL deposition to passivate the InGaAs surface, excellent sub-threshold characteristics (SSmin = 68 mV/dec) were achieved through the proposed gate stack technology. We performed positive-bias-temperature-instability (PBTI) measure -ments in order to ensure a reliable gate operation. The proposed bi-layer III-V gate stack achieved the excellent value of maximum gate overdrive voltage (V-OV,V-max) of 0.49 V with CET = 1.04 nm. The proposed gate stack has a great potential for III-V MOSFET technology to low power logic applications. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | CMOS TECHNOLOGY | - |
dc.title | Characterization of High-Performance InGaAs QW-MOSFETs With Reliable Bi-Layer HfOxNy Gate Stack | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Cha, Ho-Young | - |
dc.identifier.doi | 10.1109/JEDS.2019.2934745 | - |
dc.identifier.scopusid | 2-s2.0-85089957442 | - |
dc.identifier.wosid | 000484294100004 | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.7, no.1, pp.908 - 913 | - |
dc.relation.isPartOf | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | - |
dc.citation.title | IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY | - |
dc.citation.volume | 7 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 908 | - |
dc.citation.endPage | 913 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordPlus | CMOS TECHNOLOGY | - |
dc.subject.keywordAuthor | Indium gallium arsenide (InGaAs) | - |
dc.subject.keywordAuthor | III-V MOSFET | - |
dc.subject.keywordAuthor | high-k gate dielectric | - |
dc.subject.keywordAuthor | hafnium oxynitride (HfOxNy) | - |
dc.subject.keywordAuthor | PBTI reliability | - |
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