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A VLSI design of hierarchical search motion estimation processor chip
- Issue Date
- 1999
- Publisher
- Institute of Electrical and Electronics Engineers Inc.
- Citation
- AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, pp.247 - 249
- Journal Title
- AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
- Start Page
- 247
- End Page
- 249
- ISSN
- 0000-0000
- Abstract
- This paper presents a motion estimation processor that has regular and simple structure and achieves 100% hardware utilization without image data fill time. It can compute half-pel precision estimation and I/O bottleneck is eliminated using a small distributed on-chip image memory. The number of processing elements is scalable according to the degree of parallel processing and throughput requirements. It has been designed and verified with C++ and VHDL. © 1999 IEEE.
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Related Researcher
- You, Jae hee
- Engineering (Electronic & Electrical Engineering)