A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Jin, J. | - |
dc.contributor.author | Kim, S. | - |
dc.contributor.author | Choi, S. | - |
dc.contributor.author | Lee, P.-H. | - |
dc.contributor.author | Rhee, S.-J. | - |
dc.contributor.author | Choi, K.-H. | - |
dc.contributor.author | Kim, J. | - |
dc.date.accessioned | 2022-05-23T05:48:27Z | - |
dc.date.available | 2022-05-23T05:48:27Z | - |
dc.date.created | 2022-05-23 | - |
dc.date.issued | 2021 | - |
dc.identifier.issn | 0000-0000 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/27835 | - |
dc.description.abstract | A 7.68 GHz fast-lock digital multiplying delay-locked loop (MDLL) is presented. Implemented in a 40-nm 1.2-V CMOS process, the proposed MDLL achieves an output frequency of 7.68 GH with a high frequency multiplication factor N = 64. By adopting a cyclic Vernier TDC, the proposed MDLL achieves a fast lock time of 6 reference cycles. To reduce jitter integration caused by power supply noise, a differential pair based digitally controlled oscillator (DCO) is adopted. Also, to reduce deterministic jitter, a DSM-based dithering jitter reduction scheme has been adopted. The proposed MDLL achieves a simulated p-p jitter of about 16 ps at 7.68 GHz. It occupies an active area of 0.026 mm2, and dissipates 29 mW at 7.68 GHz. © 2021 IEEE. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
dc.title | A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, J. | - |
dc.identifier.doi | 10.1109/ISOCC53507.2021.9613940 | - |
dc.identifier.scopusid | 2-s2.0-85123355656 | - |
dc.identifier.wosid | 000861550500135 | - |
dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2021, ISOCC 2021, pp.311 - 312 | - |
dc.relation.isPartOf | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.title | Proceedings - International SoC Design Conference 2021, ISOCC 2021 | - |
dc.citation.startPage | 311 | - |
dc.citation.endPage | 312 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 1 | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Clock Generator | - |
dc.subject.keywordAuthor | Frequency Multiplication | - |
dc.subject.keywordAuthor | MDLL | - |
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