Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Cho, Mannhee | - |
dc.contributor.author | Kim, Youngmin | - |
dc.date.accessioned | 2022-05-23T08:49:47Z | - |
dc.date.available | 2022-05-23T08:49:47Z | - |
dc.date.created | 2022-05-23 | - |
dc.date.issued | 2020 | - |
dc.identifier.issn | 2163-9612 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/28004 | - |
dc.description.abstract | Content Addressable Memory (CAM) is a type of memory that searches its contents with data and outputs addresses of matching words. Conventional CAM designs used dynamic CMOS architecture for high match speed and high density, but such implementation requires use of system clocks, and thus suffer from timing violations and design limitations such as charge sharing. In this paper, we propose static based architecture for low-power high-speed Ternary CAM (TCAM), using Nanoelectromechanical (NEM) Memory Switch for nonvolatile data storage. We build 10-bits TCAM word array based on NEM Memory Switch with benefit of low power consumption and low chip density. We design the proposed TCAM architecture on commercial 65-nm process with 1.2 V operating voltage. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | Nanoelectromechanical Memory Switch based Ternary Content-Addressable Memory | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Youngmin | - |
dc.identifier.doi | 10.1109/ISOCC50952.2020.9332924 | - |
dc.identifier.scopusid | 2-s2.0-85100705977 | - |
dc.identifier.wosid | 000680824100130 | - |
dc.identifier.bibliographicCitation | 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), pp.274 - 275 | - |
dc.relation.isPartOf | 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | - |
dc.citation.title | 2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | - |
dc.citation.startPage | 274 | - |
dc.citation.endPage | 275 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 3 | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Ternary Content Addressable Memory | - |
dc.subject.keywordAuthor | Nanoelectromechanical Memory Switch | - |
dc.subject.keywordAuthor | 65-nm process | - |
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