FPGA reverse engineering in Vivado design suite based on X-ray project
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yu, Hoyoung | - |
dc.contributor.author | Lee, Hyung-Min | - |
dc.contributor.author | Shin, Youngjoo | - |
dc.contributor.author | Kim, Youngmin | - |
dc.date.accessioned | 2022-05-24T02:47:49Z | - |
dc.date.available | 2022-05-24T02:47:49Z | - |
dc.date.created | 2022-05-24 | - |
dc.date.issued | 2019 | - |
dc.identifier.issn | 2163-9612 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/28035 | - |
dc.description.abstract | As FPGA demand grows, interest in FPGA security is also increasing. FPGA Reverse Engineering (RE) in the ISE Design Suite environment has been studied extensively, but FPGA RE in the Vivado Design Suite environment has not been practically studied at present. Particularly, there is no research on Programmable Interconnect Points (PIP). Since a method that correlates bitstream and XDL file is not applicable in Vivado environment, it requires complete analysis of FPGA structure and bitstream. So X-ray project Ill is used for structure analysis. In this paper, we analyze PIP bitstream configuration information based on X-ray project and propose PIP RE method in Vivado Design Suite environment based on it. The proposed method can be extended to full FPGA RE in Vivado Design Suite environment through further studies. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE | - |
dc.title | FPGA reverse engineering in Vivado design suite based on X-ray project | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Kim, Youngmin | - |
dc.identifier.wosid | 000694734600035 | - |
dc.identifier.bibliographicCitation | 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), pp.239 - 240 | - |
dc.relation.isPartOf | 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | - |
dc.citation.title | 2019 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC) | - |
dc.citation.startPage | 239 | - |
dc.citation.endPage | 240 | - |
dc.type.rims | ART | - |
dc.type.docType | Proceedings Paper | - |
dc.description.journalClass | 3 | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | FPGA | - |
dc.subject.keywordAuthor | Reverse engineering | - |
dc.subject.keywordAuthor | non-invasive attack | - |
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