A Low-Power SerDes for High-Speed On-Chip Networks

Abstract

This paper presents a 32:1 muxing and 1:32 demuxing serializer/deserializer (SerDes) for low-power on-chip networks. The proposed deserializer employs a digital clock and data recovery (CDR) and uses a multiplying delay-locked loop (MDLL) based frequency multiplier to provide a reference clock for the CDR. The proposed SerDes and MDLL, implemented in a 65 nm CMOS process, achieves a measured data rate of 3.52 Gbps while performing 32:1 parallel-to-serial multiplexing and 1:32 serial-to-parallel de-multiplexing conversion. It occupies an active area of 0.19 mm 2 and consumes 14 mW of power.