ERROR ANALYSIS FOR PIEZORESISTIVE STRESS SENSORS USED IN FLIP CHIP PACKAGING

Abstract

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Past studies of many sources of error have led to rosette optimization and demonstrated that temperature-compensated stress extraction should be used whenever possible. In this work, we extend the error analysis to include the inherent uncertainty in the measured values of the sensor resistances and the temperature at time of the measurement. The stresses in an under-filled flip chip package are calculated using finite element simulation and utilized to evaluate the stress dependent sensitivities across the die surface. Monte Carlo simulation results confirm that temperature compensated rosette configurations should be utilized whenever possible.