A defect-tolerant memory architecture for molecular electronics

Abstract

This paper presents a defect-tolerant memory architecture for molecular electronics. An augmented crossbar-based memory, where molecules are sandwiched between nanowires, is used as a model to achieve defect tolerance. Defects in the logic circuits for addressing memory are also taken into account. The number of spare rows and columns to form a functioning memory is estimated by computer simulation for various values of defect rate and memory size.