A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, S. | - |
dc.contributor.author | Jin, J. | - |
dc.contributor.author | Kim, J. | - |
dc.date.accessioned | 2022-11-24T07:41:17Z | - |
dc.date.available | 2022-11-24T07:41:17Z | - |
dc.date.issued | 2022-11-01 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/30589 | - |
dc.description.abstract | A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz. © 2022 by the authors. | - |
dc.language | 영어 | - |
dc.language.iso | ENG | - |
dc.publisher | MDPI | - |
dc.title | A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications | - |
dc.type | Article | - |
dc.publisher.location | 스위스 | - |
dc.identifier.doi | 10.3390/electronics11213630 | - |
dc.identifier.scopusid | 2-s2.0-85141834306 | - |
dc.identifier.wosid | 000883867700001 | - |
dc.identifier.bibliographicCitation | Electronics (Switzerland), v.11, no.21 | - |
dc.citation.title | Electronics (Switzerland) | - |
dc.citation.volume | 11 | - |
dc.citation.number | 21 | - |
dc.type.docType | Article | - |
dc.description.isOpenAccess | Y | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalResearchArea | Physics | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Information Systems | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalWebOfScienceCategory | Physics, Applied | - |
dc.subject.keywordAuthor | automatic test | - |
dc.subject.keywordAuthor | built-off-test | - |
dc.subject.keywordAuthor | jitter attenuator | - |
dc.subject.keywordAuthor | jitter cleaner | - |
dc.subject.keywordAuthor | MDLL | - |
dc.subject.keywordAuthor | phase interpolator | - |
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