High-Density 1R/1W Dual-Port Spin-Transfer Torque MRAMopen access
- Authors
- Seo, Y.; Kwon, K.-W.
- Issue Date
- 1-Dec-2022
- Publisher
- MDPI
- Keywords
- 1-Read/1-Write; area optimization; bit interleaving; dual port; simultaneous access conflict; STT-MRAM
- Citation
- Micromachines, v.13, no.12
- Journal Title
- Micromachines
- Volume
- 13
- Number
- 12
- URI
- https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/30723
- DOI
- 10.3390/mi13122224
- ISSN
- 2072-666X
2072-666X
- Abstract
- Spin-transfer torque magnetic random-access memory (STT-MRAM) has several desirable features, such as non-volatility, high integration density, and near-zero leakage power. However, it is challenging to adopt STT-MRAM in a wide range of memory applications owing to the long write latency and a tradeoff between read stability and write ability. To mitigate these issues, an STT-MRAM bit cell can be designed with two transistors to support multiple ports, as well as the independent optimization of read stability and write ability. The multi-port STT-MRAM, however, is achieved at the expense of a higher area requirement due to an additional transistor per cell. In this work, we propose an area-efficient design of 1R/1W dual-port STT-MRAM that shares a bitline between two adjacent bit cells. We identify that the bitline sharing may cause simultaneous access conflicts, which can be effectively alleviated by using the bit-interleaving architecture with a long interleaving distance and the sufficient number of word lines per memory bank. We report various metrics of the proposed design based on the bit cell design using a 45 nm process. Compared to a standard single-port STT-MRAM, the proposed design shows a 15% lower read power and a 19% higher read-disturb margin. Compared with prior work on the 1R/1W dual-port STT-MRAM, the proposed design improves the area by 25%. © 2022 by the authors.
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