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A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Jung, J. | - |
| dc.contributor.author | Kim, Y. | - |
| dc.date.accessioned | 2023-02-28T01:43:13Z | - |
| dc.date.available | 2023-02-28T01:43:13Z | - |
| dc.date.created | 2023-02-28 | - |
| dc.date.issued | 2022-01-01 | - |
| dc.identifier.issn | 0000-0000 | - |
| dc.identifier.uri | https://scholarworks.bwise.kr/hongik/handle/2020.sw.hongik/30882 | - |
| dc.description.abstract | As the amount of data increases in the era of artificial intelligence (AI), in-memory computing (IMC) circuits are being studied to solve the von Neumann bottleneck, a problem in modern computer architecture. This paper proposes an XOR operator based on 8+T differential static random-access memory (8+T SRAM) and an 8-bit Full-Adder based on it. Simulation results in 65 nm show that the XOR operation is 47% faster than the previous method, the Full-Adder is 43% faster, consumes 32% less energy with 14% less transistor. © 2022 IEEE. | - |
| dc.language | 영어 | - |
| dc.language.iso | en | - |
| dc.publisher | Institute of Electrical and Electronics Engineers Inc. | - |
| dc.title | A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory | - |
| dc.type | Article | - |
| dc.contributor.affiliatedAuthor | Kim, Y. | - |
| dc.identifier.doi | 10.1109/ISOCC56007.2022.10031417 | - |
| dc.identifier.scopusid | 2-s2.0-85148470819 | - |
| dc.identifier.wosid | 000971297000065 | - |
| dc.identifier.bibliographicCitation | Proceedings - International SoC Design Conference 2022, ISOCC 2022, pp.131 - 132 | - |
| dc.relation.isPartOf | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
| dc.citation.title | Proceedings - International SoC Design Conference 2022, ISOCC 2022 | - |
| dc.citation.startPage | 131 | - |
| dc.citation.endPage | 132 | - |
| dc.type.rims | ART | - |
| dc.type.docType | Proceedings Paper | - |
| dc.description.journalClass | 1 | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Computer Science | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture | - |
| dc.relation.journalWebOfScienceCategory | Computer Science, Theory & Methods | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.subject.keywordAuthor | Full-Adder | - |
| dc.subject.keywordAuthor | In-Memory Computing(IMC) | - |
| dc.subject.keywordAuthor | Process-in-Memory(PIM) | - |
| dc.subject.keywordAuthor | SRAM | - |
| dc.subject.keywordAuthor | XOR operator | - |
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Related Researcher
- Kim, Young min
- Engineering (Electronic & Electrical Engineering)