5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory

Abstract

A new low-power, fast-locking, all-digital delay-locked loop (DLL) that uses a disposable time-to-digital converter (TDC) is presented for future memory systems beyond double data rate 4. To achieve fast locking and high-frequency operation, the proposed DLL utilises a new hybrid (TDC + binary + sequential) search algorithm that results in a fast locking time of 11 clock cycles without the false lock and harmonic lock problems. By minimising the intrinsic delay of the digital delay line, the proposed DLL achieves an operating frequency range of 1.5-5.0 GHz which is higher than that of the current state-of-the-art all-digital DLLs. The DLL is fabricated in a 65 nm CMOS process and it achieves a peak-to-peak (p-p) output clock jitter of 14 ps (with a p-p input clock jitter of 8 ps) at 5 GHz. The DLL consumes 6.9 mW at 1 V and occupies an active area of 0.025 mm(2).