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An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis
- Issue Date
- Apr-2016
- Publisher
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- Keywords
- on-chip monitoring circuit; chip-to-chip interface; analog-to-digital converter; phase-locked loop-based frequency synthesizer; sub-sampling
- Citation
- IEICE TRANSACTIONS ON ELECTRONICS, v.E99C, no.4, pp.440 - 443
- Journal Title
- IEICE TRANSACTIONS ON ELECTRONICS
- Volume
- E99C
- Number
- 4
- Start Page
- 440
- End Page
- 443
- ISSN
- 1745-1353
- Abstract
- An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.
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Related Researcher
- JANG, YOUNG CHAN
- College of Engineering (School of Electronic Engineering)