A 20-Gb/s Receiver Bridge Chip With Auto-Skew Calibration for MIPI D-PHY Interface
- Authors
- Lee, Pil-Ho; Jang, Young-Chan
- Issue Date
- Nov-2019
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Mobile industry processor interface (MIPI); D-PHY; skew calibration; continuous time linear equalization; byte synchronization; deserialization
- Citation
- IEEE TRANSACTIONS ON CONSUMER ELECTRONICS, v.65, no.4, pp.484 - 492
- Journal Title
- IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
- Volume
- 65
- Number
- 4
- Start Page
- 484
- End Page
- 492
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/133
- DOI
- 10.1109/TCE.2019.2942503
- ISSN
- 0098-3063
- Abstract
- A 20-Gbps receiver bridge chip featuring auto-skew calibration and continuous-time linear equalization is proposed to support the mobile industry processor interface D-PHY version 2.0 specification with four data lanes and one clock lane. The proposed receiver bridge chip performs byte synchronization and 1-to-8 deserialization for converting high-speed scalable low-voltage signals into low-speed low-voltage complementary metal-oxide semiconductor signals. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise owing to the use of the multiple bits supplied from the deserializer as a result of the phase detector for the skew calibration. It is performed via a four-step sequential process to use the minimum time delay. The proposed receiver bridge chip is implemented using a 0.11 mu m CMOS process with a 1.2 V supply. The measured peak-to-peak time jitter of the signal recovered using the proposed receiver is 50 ps at a data rate of 5.0 Gbps/lane on a printed circuit board FR-4 10 inch channel. The proposed skew calibration reduces the time skew among the four data lanes and one clock lane to less than 10 ps.
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