A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization
DC Field | Value | Language |
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dc.contributor.author | Lee, Pil-Ho | - |
dc.contributor.author | Jang, Young-Chan | - |
dc.date.available | 2021-01-22T06:40:16Z | - |
dc.date.created | 2021-01-22 | - |
dc.date.issued | 2020-11 | - |
dc.identifier.issn | 1549-7747 | - |
dc.identifier.uri | https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/18557 | - |
dc.description.abstract | A 3.0 GSymbol/s/lane transceiver bridge chip, which fully supports the mobile industry processor interface (MIPI) C-PHY version 1.1 specification, is proposed for field-programmable gate array (FPGA)-based pattern generators and frame grabbers. In transmit mode, it converts parallel low-voltage complementary metal oxide semiconductor (CMOS) signals into high-speed three-level signals when performing serialization. In addition, deserialization including clock recovery from the received data is performed for its receive mode operation. A pre-emphasis transmitter and an elastic receiver that perform equalization according to the signal level are proposed to improve the signal integrity of high-speed three-level signals. The proposed MIPI C-PHY transceiver bridge chip is implemented using a 65 nm CMOS process with 1.2 V supply voltage. The area of each lane is 0.103 mm(2) and the power consumption in high-speed transmit and receive modes is 2.96 mW/Gbps/lane and 5.62 mW/Gbps/lane, respectively. The measured peak-to-peak time jitter of the proposed high-speed transmitter, receiver, and clock recovery are 0.27 UI, 0.35 UI, and 90 ps, respectively, at a data rate of 3 GSymbol/s/lane. | - |
dc.language | 영어 | - |
dc.language.iso | en | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization | - |
dc.type | Article | - |
dc.contributor.affiliatedAuthor | Lee, Pil-Ho | - |
dc.contributor.affiliatedAuthor | Jang, Young-Chan | - |
dc.identifier.doi | 10.1109/TCSII.2019.2962839 | - |
dc.identifier.wosid | 000604257500074 | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.11, pp.2672 - 2676 | - |
dc.relation.isPartOf | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | - |
dc.citation.volume | 67 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2672 | - |
dc.citation.endPage | 2676 | - |
dc.type.rims | ART | - |
dc.type.docType | Article | - |
dc.description.journalClass | 1 | - |
dc.description.isOpenAccess | N | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.subject.keywordAuthor | Clocks | - |
dc.subject.keywordAuthor | Receivers | - |
dc.subject.keywordAuthor | Transceivers | - |
dc.subject.keywordAuthor | Transmitters | - |
dc.subject.keywordAuthor | Delays | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Bridge circuits | - |
dc.subject.keywordAuthor | Clock recovery | - |
dc.subject.keywordAuthor | C-PHY | - |
dc.subject.keywordAuthor | elastic receiver | - |
dc.subject.keywordAuthor | mobile industry processor interface | - |
dc.subject.keywordAuthor | pre-emphasis transmitter | - |
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