A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization
- Authors
- Lee, Pil-Ho; Jang, Young-Chan
- Issue Date
- Nov-2020
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Keywords
- Clocks; Receivers; Transceivers; Transmitters; Delays; Jitter; Bridge circuits; Clock recovery; C-PHY; elastic receiver; mobile industry processor interface; pre-emphasis transmitter
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.67, no.11, pp.2672 - 2676
- Journal Title
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
- Volume
- 67
- Number
- 11
- Start Page
- 2672
- End Page
- 2676
- URI
- https://scholarworks.bwise.kr/kumoh/handle/2020.sw.kumoh/18557
- DOI
- 10.1109/TCSII.2019.2962839
- ISSN
- 1549-7747
- Abstract
- A 3.0 GSymbol/s/lane transceiver bridge chip, which fully supports the mobile industry processor interface (MIPI) C-PHY version 1.1 specification, is proposed for field-programmable gate array (FPGA)-based pattern generators and frame grabbers. In transmit mode, it converts parallel low-voltage complementary metal oxide semiconductor (CMOS) signals into high-speed three-level signals when performing serialization. In addition, deserialization including clock recovery from the received data is performed for its receive mode operation. A pre-emphasis transmitter and an elastic receiver that perform equalization according to the signal level are proposed to improve the signal integrity of high-speed three-level signals. The proposed MIPI C-PHY transceiver bridge chip is implemented using a 65 nm CMOS process with 1.2 V supply voltage. The area of each lane is 0.103 mm(2) and the power consumption in high-speed transmit and receive modes is 2.96 mW/Gbps/lane and 5.62 mW/Gbps/lane, respectively. The measured peak-to-peak time jitter of the proposed high-speed transmitter, receiver, and clock recovery are 0.27 UI, 0.35 UI, and 90 ps, respectively, at a data rate of 3 GSymbol/s/lane.
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